1. Field of Use
The present invention relates to data processing systems and, in particular, to cache memory systems.
2. Prior Art
It is known to provide parity check circuits for detecting errors in the addresses and information read from the directory or cache store during a read cycle of operation to generate signals which simulate a condition that the requested information was not stored in cache store although it was stored and read out. This causes a backing store cycle of operation to be initiated for read out of a correct version of the actual requested information from a backing store containing error detection and correction (EDAC) circuits. This system is disclosed in U.S. Pat. No. 4,084,236 which issued on Apr. 11, 1978.
While the above system improves the reliability of the information being provided, it presumes that the states of the cache address directory circuits are faulty. In other words, it is not very fault tolerant.
Faults are generally classified in terms of their duration, nature and extent. The duration of a fault can be transient, intermittent or permanent. A transient fault, often the result of external disturbances, exists for a finite length of time and is nonrecurring. Thus, the ability to retry or recover from such transient faults becomes important for a system to be fault tolerant.
This is particularly important in cases where the cache unit is utilized as part of a virtual memory unit, responsible for translating virtual addresses into physical addresses. Accordingly, it is a primary object of the present invention to provide a virtual memory unit which is more resilient to various types of error conditions.
It is a further, more specific object of the present invention to provide a virtual memory unit which incorporates resiliency features without increasing the complexity of the unit.